In static random access memories (SRAMs) it has been found desirable to perform various circuit functions in response to an address transition in providing data. In SRAMs which use address transition detection (ATD), there have developed problems in losing data in some situations. There are sometimes pattern sensitivities. There are sometimes address skew problems as well. Address skew occurs when more than one address changes but not quite at the same time. In typical operation, the address skew is quite small in relation to the total access time. For a typical access in a system, the address skew is typically a nanosecond (ns) or two whereas the SRAM has an access time around 35 ns SRAM. For this type of address skew, there have been few problems. Also in a typical system, however, there are occasions in which the addresses are rapidly changing for a relatively long time, for example 25 ns, before becoming valid. This is the condition in which failures have been more likely to occur. Although reasons for the occurrence of the problem have been difficult to measure, one of the causes addressed in the present invention is related to the fact that, in the typical prior art ATD memory circuit, the word lines can be activated during severe address skew. When the word line is activated, the SRAM cells that are on that row are enabled and are attempting to differentiate the voltage on the bit lines. If another word line is then accessed, the bit line may be sufficiently differentiated that the newly activated cells may have their data reversed, particularly if the cell is relatively weak. Under typical addressing situations this problem is handled by ensuring that the bit lines have been equalized before activating the next word line. Under severe address skew conditions, which are likely to occur occasionally, the bit lines may not, however, get equalized sufficiently, causing the occasional loss of data.
Another complicating factor is the desirability of turning off major portions of the memory between cycles when operating at less than the maximum cycle frequency. This is generally handled with a cycle end timer which turns off some power consuming portions at the end of a cycle. This results in significant power savings when operating at relatively low cycle rates. This does, however, add circuit complexity which can potentially add to the cycle length when there is an access after the timer has timed out.